Multi-Chip Semiconductor Devices Having Non-Volatile Memory Devices Therein

ABSTRACT

A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

REFERENCE TO PRIORITY APPLICATIONS

This application is a continuation-in-part of U.S. patent application Ser. No. 12/040,282, filed Feb. 29, 2008, which claims the benefit of Korean Patent Application No. 2007-0041415, filed Apr. 27, 2007, the disclosures of which are hereby incorporated herein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to a flash memory device and a flash memory system, and more particularly, to a flash memory device and a flash memory system in which a problem that an operating speed is lowered due to a disadvantage of a flash memory device which does not support a random access when a booting operation is performed in an electronic device system having a flash memory device to which a file system is mounted is improved.

BACKGROUND OF THE INVENTION

These days, the importance of a flash memory is increased due to remarkable development of portable multimedia devices. Of these, a NAND flash memory not only has a storage device of a high capacity but also is relatively low in price compared to other memories, and so it is suitable for a portable storage device.

On the other hand, the NAND flash memory does not support a random access which is supported by memory devices such as SRAM, DRAM, FRAM, MRAM, and PRAM, should perform a data read operation in a page unit and should perform a data write operation after erasing previous data. For these reasons, it takes a long time to write data, and an actual use of the NAND flash memory requires a lot of complementation in a software side due to a limitation to the number of data write times.

For example, data should be stored according to a certain rule in order to store and read data in a computing device, and what names a file, locates a position (directory) of a file and expresses information related to security and authority logically and physically is called a file system.

A file system designed to read and write data in a file unit for a characteristic of the NAND flash memory is a Yet Another Flash Filing System (YAFFS) which is a log-structured file system which automatically provides a wear leveling function and the strength for the power interruption.

Here, a flash memory has a limited life span that data can be recorded in each sector, and the wear leveling function is a softwarical method which prevents an electrical erasing operation for repetitively being performed for a certain sector so that an electric erasing operation can be uniformly performed for all sectors and so all sectors can be evenly used, thereby leveling a life span of all sectors.

FIG. 1 is a block diagram illustrating a conventional flash memory device having a file system mounted therein. As shown in FIG. 1, a NAND flash memory 10 and a DRAM 20 are provided. The NAND flash memory 10 comprises a plurality of page data cells 12 and a plurality of spare data cells 14.

In FIG. 1, the NAND flash memory 10 has a plurality of pages which are formed such that object headers comprised of a plurality of page data stored in a plurality of page data cells 12 match with a plurality of tags stored in a plurality of spare data cells 14 by one-to-one correspondence.

The NAND flash memory 10 stores page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written in a plurality of page data cells 12 and stores spare data such as a boot loader, an error correcting code (ECC), information about a bad block, and information about the number of deletion times in a plurality of spare data cells 14. This is because the NAND flash memory 10 allows weak cells more or less and so an additional storage space for storing these information are needed.

The DRAM 20 receives information which are stored by scanning the object header data stored in a plurality of page data cells 12 and the tag data in a plurality of spare data cells and performs an address-mapping operation for them in a tree structure when the file system is mounted in the flash memory device attached to a portable multimedia device.

However, since the flash memory device can not support a random access, in order to boot the flash memory device mounted onto the system, relevant data are first copied to the DRAM 20 which supports a random access, and then a central processing unit (CPU) accesses the DRAM 20 to perform a program.

At this time, a mounting time is very long since the DRAM 20 scans data in the NAND flash memory 10 to select a file, and a data erase operation should be performed in advance before recording data in order to record data, and a softwarical complementation such as a wear leveling for levelly recording data in the whole flash memory is needed due to a garbage collection for reducing a recording time and a limitation to the number of recording times.

Here, the garbage collection is a task for gathering garbage areas of a storage device so that a program can use them, and the garbage area is an area which is actually not being used and can not be used by another program since a user program asks a storage device to use a certain area necessary for an operating system but does not return the area even after finishing a use of the area.

FIG. 2 is a block diagram illustrating a booting operation of a NAND chip which improves reading and writing speeds of the conventional flash memory device. As shown in FIG. 2, a NAND flash memory 10, an SRAM 30, and a control logic portion 40, a memory controller 70 are provided. The NAND flash memory 10 comprises a plurality of page data cells and a plurality of spare data cells.

Functions of the components which perform a booting operation of the NAND chip are described below with reference to FIG. 2.

The NAND flash memory 10 stores page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written in a plurality of page data cells and stores spare data such as a boot loader, an ECC, information about a bad block, and information about the number of deletion times in a plurality of spare data cells.

The SRAM 30 receives the booting code dumped from the boot loader stored in a plurality of spare data cells of the NAND flash memory 10 to store the information while serving as a data write and read buffer.

The control logic portion 40 comprises a register, an ECC circuit, and an address generating circuit. The control logic portion 40 stores an address and a command provided outside the chip, corrects a one-bit error when data are transferred to the SRAM 30 from the NAND flash memory 10, and receives an initial address of data to be read and then automatically generates addresses and store them in the SRAM 30 again.

The memory controller 70 receives the booting code which is dumped to and temporarily stored in the SRAM 30 to boot a corresponding operating system of an electronic device system by using a predetermined booting program and provides address information containing an initial address of read data and a command to the control logic portion 40. That is, the memory controller 70 overally controls an operation of the NAND chip.

A file system mounting and booting operation of the NAND chip is described below with reference to FIGS. 1 and 2.

For better understanding, let us assume that an operating system specific to an electron device system such as a portable computer (PC) or a portable multimedia device is booted after the flash memory device is attached to the electronic device system and then the file system is mounted onto the flash memory device.

The NAND flash memory 10 stores page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written in a plurality of page data cells and stores spare data such as a boot loader, an ECC, information about a bad block, and information about the number of deletion times in a plurality of spare data cells.

The DRAM 20 receives information which are stored by scanning the object header data stored in a plurality of page data cells and the tag data in a plurality of spare data cells and performs an address-mapping operation for them in a tree structure when the file system of the flash memory device is mounted.

The SRAM 30 receives the booting code dumped from the boot loader stored in a plurality of spare data cells of the NAND flash memory 10 to temporarily store the information, and the control logic portion 40 stores an address and a command provided from the memory controller 70, receives an initial address of data to be read, and then automatically generates addresses and store them in the SRAM 30 again.

The memory controller 70 receives the booting code which is dumped to and temporarily stored in the SRAM 30 to boot a corresponding operating system of the electronic device system by using a predetermined booting program.

Meanwhile, the flash memory has a limited life span that data can be recorded in each sector, the life span closely relates to the number of times of electrical erase performed for each sector, and if the number of electrical erase times exceeds a predetermined value, there may occur an error in recording data.

In order to extend the life span of the flash memory, the number of erase times of the NAND flash memory 10 and a block setting of the NAND flash memory 10 to be deleted are controlled. The conventional NAND chip separately needs areas in the NAND flash memory 10 for a plurality of spare data cells which store a boot loader, an ECC, information about a bad block, and information about the number of deletion times and also needs a process for temporarily storing information such as the ECC, the information about the bad block and information about the number of deletion times in the DRAM 20 and a process for dumping the booting code stored in a plurality of spare data cells from the boot loader to the SRAM 30 when the electronic device system is booted.

For these reasons, a speed for writing/reading data onto/from the NAND flash memory 10 is slow, and there is a problem in that data may be lost when powered off because the SRAM 30 temporarily store data as the data write and read buffer.

FIG. 3 is a block diagram illustrating a flash memory system with a conventional NAND flash memory. The flash memory system of FIG. 3 comprises a latching and decoding portion 15, a control logic 25, a NAND flash memory cell array 35, a NAND flash page buffer 45, a NAND flash column selecting portion 55, a buffer portion 65, an SRAM 75, a memory bus 60, a memory controller 70, and a CPU 80. The NAND flash memory cell array 35 is divided into a plurality of pages which comprise a plurality of page data cells and a plurality of spare data cells, each page comprises one or more sectors, and each sector comprises a plurality of memory cells.

An operation of the conventional NAND flash memory system is described below with reference to FIG. 3.

When address information ADD and a command COM are applied from the electronic device system, the latching and decoding portion 15 latches, decodes and stores the information. The address information ADD contains a row address, a column address, a sector address, information about the number of sectors, and a page address. The command COM contains read and write commands, a program command, and an erase command.

The control logic 25 overally controls an operation of the flash memory device according to which command the command COM stored in the latching and decoding portion 15 represents, and controls the NAND flash page buffer portion 45 according to the sector address and the information about of the number of sectors provided from the latching and decoding portion 15. For example, in case of desiring to read data corresponding to one sector in the NAND flash memory cell array 35, the control logic 25 controls the NAND flash page buffer portion 45 so that only the page buffers belonging to the selected sector can perform the read operation.

The NAND flash page buffer portion 45 comprises a plurality of page buffers which respectively correspond to columns of the NAND flash memory cell array 35, and reads data from the NAND flash memory cell array 35 under control of the control logic 60 during the read operation and temporarily stores the read data. The data may contain spare data as well as page data.

In response to a control operation of the control logic 25, the NAND flash column selecting portion 55 sequentially selects the page buffers of the NAND flash page buffer portion 45 in a certain unit according to the column address information ADD from the latching and decoding portion 15 and then outputs data bits of the selected page buffers.

The buffer portion 65 temporarily stores the data bits transmitted through the NAND flash column selecting portion 55 and outputs stored data DO under control of the control logic 25 when data of one page stored in the NAND flash page buffer portion 45 are inputted.

As the data write and read buffer, the SRAM 75 receives data through the memory bus and transfers the data to the buffer portion 65 when the write command is applied or receives page data stored in the page data cells in the NAND flash memory cell array 35 and outputs the page data outside the memory system while receiving the boot code which is stored in the spare data cells and dumped from the boot loader and temporarily storing the information.

The memory controller 70 provides the address information and the command to the flash memory device through the memory bus 60 and overally controls an operation of the flash memory device.

The CPU 80 executes an internal booting program to boot a corresponding operating system of the electronic device system by using the booting code which is copied to the SRAM which supports a random access since the flash memory device can not support a random access.

As described above, in the conventional NAND flash memory device and the flash memory system, a plurality of spare data cells are located in the same row as a plurality of page data cells so that all of a plurality of page data cell areas and all of a plurality of spare data cell areas are selected by one row address, and they operates by distinguishing page data and spare data by using the column address.

When a defective block is found by testing the NAND flash memory 10, an operation for setting it as a defective block through defective block information of a plurality of spare data cells is performed, and there is a problem in that the erasing and writing speed is slow since a plurality of spare data cell areas comprise the NAND flash memory cell.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a flash memory device in which a limitation of a conventional flash memory device which is impossible to randomly access when a booting operation is performed in an electronic device system having a flash memory device to which a file system is mounted is got over and a non-volatile memory device used as a read or write buffer is integrated therein.

It is an object of the present invention to provide a flash memory system in which a limitation of a conventional flash memory device which is impossible to randomly access when a booting operation is performed in an electronic device system having a flash memory device to which a file system is mounted is got over and a non-volatile memory device used as a read or write buffer is integrated therein.

One aspect of the present invention provides a flash memory device, comprising: a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

The second non-volatile memory is used as a data write and read buffer while loading a boot loader of an electronic device system to the second non-volatile memory to perform a booting operation.

Each of the plurality of page data cells and each of the plurality of spare data cells are combined to constitute one page, the page comprises at least one sector, and each sector comprises a plurality of memory cells.

The second non-volatile memory comprises a logic portion which controls a wear leveling function and a garbage collecting function which are necessary during a write operation of the first non-volatile memory and controls the number of erase times of the first non-volatile memory cell and a block setting of the first non-volatile memory to be deleted, in the second non-volatile memory region.

The first non-volatile memory is a NAND flash memory, and the second non-volatile memory is any of a FRAM, a PRAM, an MRAM, and a RRAM.

The logic portion is realized by a discrete chip in a multi-layer chip package form above an integrated circuit of a one-chip form of the first and second non-volatile memories.

The page data are data which have information including the size of data and a file to be written from an external portion and information as to whether data are read or written, and the spare data are data which have information including a boot loader, an error correction code (ECC), information about a bad block, and information about the number of deletion times.

Another aspect of the present invention provides a flash memory system, comprising: a flash memory device which stores page data in a plurality of page data cells and spare data in a plurality of spare data, reads the stored page data and the stored read data when a read command is applied from an external portion, and sequentially selecting a plurality of first or second page buffers according to address information applied from the external portion to output data; a central processing device which receives the spare data and executes a stored booting program to boot an operating system of an electronic device system; a memory controller which provides address information and a command to the flash memory device and controls an overall operation of the flash memory device; and a memory bus which serves as a medium for transmitting data, address information and a command between the flash memory device and the memory controller.

The flash memory device comprises a latching and decoding portion for receiving address information and a command from an external portion, and latching and decoding the address information and the command; a first non-volatile memory including the plurality of page data cells and the plurality of first page buffers, storing page data in the plurality of page data cells, and sequentially selecting the plurality of first page buffers according to the address information to output data when a read command is applied from the external portion; a second non-volatile memory including the plurality of spare data cells respectively adjacent the plurality of page data cells and the plurality of second page buffers, storing the spare data in the plurality of spare data cells, scanning the spare data to temporarily corresponding information when a file system is mounted, and sequentially selecting the plurality of second page buffers to output data according to the address information when the read command is applied; and a control logic which controls overall operations of the first and second non-volatile memories in response to the decoded address information and the decoded command.

The first non-volatile memory comprises a first non-volatile memory cell array which includes the plurality of page data cells and stores the page data; a first page buffer portion which includes the plurality of first page buffers respectively corresponding to columns of the first non-volatile memory cell array, and reading and temporarily storing data from the first non-volatile memory cell array in response to control of the control logic when the read command is applied; and a NAND flash column selecting portion which outputs the temporarily stored page data to the selected first page buffers after sequentially selecting the plurality of first page buffers according to the decoded address information in response to control of the control logic.

The second non-volatile memory further comprises a second non-volatile memory cell array which includes a plurality of spare data cells which have the same row address as and are adjacent to the plurality of page data cells, respectively, and stores the spare data; a second page buffer portion which includes the plurality of second page buffers respectively corresponding to columns of the second non-volatile memory cell array, and reads and temporarily stores the spare data from the second non-volatile memory cell array in response to control of the control logic when the read command is applied; a second non-volatile memory cell column selecting portion which outputs the temporarily stored data to the selected page buffers after sequentially selecting the plurality of second page buffers according to the decoded address information in response to control of the control logic; a second non-volatile memory control portion which receives the decoded command from the control logic to output a second non-volatile memory control signal to overally control read and write operations of the second non-volatile memory; and a second non-volatile memory row decoder which receives the latched address information and decodes a row address of the second non-volatile memory to have the same address as a row address for selecting a page in the page data cell.

The flash memory device further comprises a buffer portion which receives data to be programmed in the first non-volatile memory cell array from the electronic device system and temporarily stores the data, and transmits the data to the first page buffer portion in response to control of the control logic, and also receives and temporarily stores page data of the selected first page buffers and spare data of the selected second page buffers and outputs the page data and the spare data which are temporarily stored to an external portion in response to control of the control logic.

The second non-volatile memory does not load a boot loader of the electronic device system to a discrete semiconductor memory device which supports a random access but performs a booting operation in the second non-volatile memory while being used as a data write and read buffer.

The first non-volatile memory is a NAND flash memory, and the second non-volatile memory is any of a FRAM, a PRAM, an MRAM, and a RRAM.

Each of the plurality of page data cells and each of the plurality of spare data cells are combined to constitute one page, the page comprises at least one sector, and each sector comprises a plurality of memory cells.

The address information comprises a row address, a column address, a sector address, information about the number of sectors, and a page address, and the command comprises a read command, a program command, and an erase command.

The page data are data which have information including the size of data and a file to be written from an external portion and information as to whether data are read or written, and the spare data are data which have information including a boot loader, an error correction code (ECC), information about a bad block, and information about the number of deletion times.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a block diagram illustrating a conventional flash memory device having a file system mounted therein;

FIG. 2 is a block diagram illustrating a booting operation of a NAND chip which improves reading and writing speeds of the conventional flash memory device;

FIG. 3 is a block diagram illustrating a flash memory system with a conventional NAND flash memory;

FIG. 4 is a block diagram illustrating a flash memory device having a file system mounted therein according to an exemplary embodiment of the present invention;

FIG. 5 is a block diagram illustrating a booting operation of the flash memory device of the present invention in which the NAND flash memory and the FRAM are integrated into a one chip;

FIG. 6 is a block diagram illustrating a flash memory device according to the exemplary embodiment of the present invention;

FIG. 7 is a block diagram illustrating a flash memory system with the flash memory device according to the exemplary embodiment of the present invention;

FIG. 8 illustrates a flash memory device implemented in the form of a multi-chip package according to the exemplary embodiment of the present invention;

FIG. 9 illustrates a through silicon via (TSV) of a multi-chip package semiconductor device according to the exemplary embodiment of the present invention; and

FIG. 10 shows a portion of a chip of FIG. 9, illustrating a conductive pillar including a TSV and a conductive socket in detail.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout the specification.

FIG. 4 is a block diagram illustrating a flash memory device having a file system mounted therein according to an exemplary embodiment of the present invention. As shown in FIG. 4, a flash memory device 100 and a DRAM 20 are provided. The flash memory device 100 comprises a NAND flash memory 120 for storing page data and a ferroelectric random access memory (FRAM) 140 for storing spare data.

A plurality of pages are formed such that object headers which comprise a plurality of page data stored in the NAND flash memory 120 match with a plurality of tags stored in the FRAM 140 by one-to-one correspondence.

Compared to the conventional flash memory device of FIG. 1, the flash memory device of FIG. 4 is same in a standpoint that page data such as the size of data and a file to be written from an external portion and information as to whether data are read or written which are stored in a data area are stored in the NAND flash memory 120, but it is different in a standpoint that spare data such as a boot loader, an error correcting code (ECC), information about a bad block, and information about the number of deletion times are stored in a discrete FRAM 140 cell instead of a plurality of spare data cells of the NAND flash memory 120.

Functions of the components of FIG. 4 are described below.

The NAND flash memory 120 comprises a plurality of page data cells, stores page data and then reads the stored page data to output data when a read command is applied from the external portion.

The FRAM 140 comprises a plurality of spare data cells, which respectively have the same row address as and are adjacent to a plurality of page data cells, stores spare data, then scans the spare data to temporarily store corresponding information by itself, and reads and outputs the stored spare data when the read command is applied.

When the flash memory device is installed in the electronic device and the file system is mounted on the flash memory device, a mounting time can be significantly reduced by scanning information the spare data cell area of the FRAM 140 which is a non-volatile RAM which is faster in a read and write time than the conventional flash memory device which scans data of the NAND flash memory 120 area due to a limitation of the flash memory device that a random access is impossible.

In general, the FRAM randomly accesses data to read the data and writes data without erasing the data, and thus its data access time is 1,000 time faster than the NAND flash memory.

FIG. 5 is a block diagram illustrating a booting operation of the flash memory device of the present invention in which the NAND flash memory and the FRAM are integrated into a one chip. The flash memory device of FIG. 5 comprises the NAND flash memory 120, the FRAM 140, and a memory controller 200.

Functions of the components of FIG. 5 are described below.

The NAND flash memory 120 comprises a plurality of page data cells, stores page data such as the size of data and a file to be written from the external portion and information as to whether data are read or written, and then reads the stored page data to output data when a read command is applied from the external portion.

The FRAM 140 stores spare data such as a boot loader, an ECC, information about a bad block, and information about the number of deletion times and serves as a data write and read buffer.

The memory controller 200 overally controls an operation of the flash memory device 100, for example, it provides address information and a command to the NAND flash memory 120 and the FRAM 140.

Therefore, the boot loader for a booting is stored in the non-volatile RAM and is used in a personal computer (PC) or a portable multimedia device, and an eXecute In Place (XIP) function for performing a booting on the non-volatile RAM “as is” is realized without loading the boot loader which is a booting program, whereby a booting time can be significantly reduced, and also the non-volatile RAM is used as the data read/write buffer, and so data are not lost even when powered off, whereby an operating performance of the NAND flash memory 120 can be significantly improved.

That is, differently from the conventional flash memory device in which when the flash memory device is attached to the system to perform a booting since it can not support a random access, the booting code is copied to the SRAM which supports a random access and the CPU accesses the SRAM to execute the program, according to the flash memory device of the present invention, the CPU executes the booting program by using the booting code stored in the FRAM 140 in the flash memory device.

Also, since the NAND flash memory 120 and the FAM 140 are integrated into a one chip, the ECC of the NAND flash memory 120 cell or the information about the bad block can be stored directly in the FRAM 140 during the memory test process, so that there is a need for discretely preparing for a plurality of spare data cell areas in the NAND flash memory 120.

A file system mounting and booting operation of the flash memory device according to the present invention is described below with reference to FIGS. 4 and 5.

For better understanding, let us assume that an operating system specific to an electron device system such as a portable computer (PC) or a portable multimedia device is booted after the flash memory device is attached to the electronic device system and then the file system is mounted onto the flash memory device.

The NAND flash memory 120 stores page data such as the size of data and a file to be written from the external portion and information as to whether data are read or written in a plurality of page data cells, and the FRAM 140 stores spare data such as a boot loader, an ECC, information about a bad block, and information about the number of deletion times in a plurality of spare data cells.

When the file system of the flash memory device 100 is mounted, the FRAM 140 receives information which are stored by scanning the object header data stored in a plurality of page data cells and the tag data in a plurality of spare data cells and performs an address-mapping operation for them in a tree structure.

The FRAM 140 temporarily stores the information by using the booting code through the boot loader stored in a plurality of spare data cells therein, and the control logic portion stores an address and a command provided from the memory controller 200, receives the initial address of data to be read, and automatically generates the next addresses and stores them in the FRAM 140 again.

The memory controller 200 overally controls an operation of the flash memory device 100, for example, it provides address information and a command to the NAND flash memory 120 and the FRAM 140.

FIG. 6 is a block diagram illustrating a flash memory device according to the exemplary embodiment of the present invention. The flash memory device of FIG. 6 comprises the NAND flash memory 120 and the FRAM 140. The NAND flash memory 120 comprises a plurality of page data cells 122, and the FRAM 140 comprises a plurality of spare data cells 142 and a logic portion 144.

Functions of the components of FIG. 6 are described below.

Functions of the NAND flash memory 120 and the FRAM 140 are identical to those of the flash memory device of FIG. 5 in which the NAND flash memory 120 and the FRAM 140 are integrated into a one chip, and thus descriptions on those are omitted.

The logic portion 144 controls a wear leveling function and a garbage collecting function which are necessary during a write operation of the NAND flash memory 120 and controls the number of erase times of the NAND flash memory 120 and a block setting of the NAND flash memory 120 to be deleted by using the FRAM 140 having information about a plurality of spare data cells 142 stored therein or other storage areas of the FRAM 140.

Here, it is possible to realize the logic portion 144 with a discrete chip on the flash memory device 100 in which the NAND flash memory 120 and the FRAM 140 are integrated into a one chip in a multi-chip package (MCP) form.

FIG. 7 is a block diagram illustrating a flash memory system with the flash memory device according to the exemplary embodiment of the present invention. The flash memory system of FIG. 7 comprises a NAND flash memory cell array 35, a NAND flash page buffer portion 45, a NAND flash column selecting portion 55, a buffer portion 650, a latch and decoding portion 150, a control logic 250, a FRAM cell array 350, a FRAM page buffer 450, a FRAM column selecting portion 550, a FRAM control portion. 750, a FRAM row decoder 850, a memory bus 600, a memory controller 200, and a CPU 800.

The NAND flash memory cell array 35 is divided into a plurality of pages which comprise a plurality of page data cells 122, the FRAM cell array 350 is divided into a plurality of pages which comprise a plurality of spare data cells 142, each page comprises one or more sectors, and each sector comprises memory cells of plural-bytes.

Functions of the components of FIG. 7 are described below.

The NAND flash memory cell array 35 stores data such as the size of data and a file to be written from the external portion, and information as to whether data are read or written, and the FRAM cell array 350 replaces a plurality of spare data cells in the conventional flash memory and is same in storing a boot loader, an ECC, information about a bad block, and information about the number of deletion times, but it is different in a standpoint that the read speed is faster and data can be written without erasing the previous data.

The NAND flash page buffer portion 45 and the FRAM page buffer portion 450 comprises page buffers which respectively correspond to columns of the NAND flash memory cell array 35 and the FRAM cell array 350, respectively, read data from the NAND flash memory cell array 35 or the FRAM cell array 350 under control of control logic 250 during the read operation and temporarily store the read data.

The NAND flash column selecting portion 55 and the FRAM column selecting portion 550 sequentially select page buffers of the NAND flash page buffer portion 45 and the FRAM page buffer portion 450 before outputting data bits of the selected page buffers according to the column address information from the latching and decoding portion 150 in response to the control of the control logic 250, respectively.

The buffer portion 650 temporarily stores the data bits transmitted through the NAND flash column selecting portion 55 and the FRAM column selecting portion 550 and outputs stored data DO to the external portion under control of the control logic 250 when data of one page stored in the NAND flash page buffer portion 45 and the FRAM page buffer portion 450 are inputted. The buffer portion 650 temporarily stores data to be programmed in the NAND flash memory cell array 35 from the electronic device system and then transfers them to the NAND flash page buffer portion 45 through the NAND flash column selecting portion 55.

The latching and decoding portion 150 receives, latches, decodes and stores address information ADD and a command COM from the electronic device system. The address information ADD contains a row address, a column address, a sector address, information about the number of sectors, and a page address. The command COM contains read and write commands, a program command, ad an erase command.

The control logic 250 controls an overall operation of the flash memory device 100 according to which of read, program and erase commands the command COM stored in the latching and decoding portion 150 represents, and controls the NAND flash page buffer portion 45 and the FRAM page buffer portion 450 according to the sector address and the information about the number of sectors provided from the latching and decoding portion 150.

For example, in case of desiring to read data corresponding to one sector, the control logic 25 controls the NAND flash page buffer portion 45 and the FRAM page buffer 450 so that only the page buffers belonging to the selected sector can perform the read operation.

The FRAM control portion 750 receives a discrete non-volatile memory control signal from the control logic 250 to control the read and write operations of the FRAM 140 since the read and write operations of the FRAM 140 are different from those of the NAND flash memory.

The FRAM row decoder 850 decodes a row address of the FRAM cell to have the same address as a row address for selecting a page in a plurality of page data cells 122.

The FRAM column selecting portion 550 receives a discrete non-volatile memory control signal from the control logic to decode a column address of the FRAM cell since the read and write speeds are much faster than those of the NAND flash memory.

The CPU 80 executes the booting program by using the booting code stored in the FRAM cell array 350 which supports a random access to boot a corresponding operating system of the electronic device system.

The memory controller 200 controls an overall operation of the flash memory device, for example, it provides address information and a command to the NAND flash memory and the FRAM.

The memory bus 60 transfers data, address information and a command between the NAND flash memory and the FRAM and the memory controller.

An operation of the flash memory system according to the exemplary embodiment of the present invention is described below with reference to FIG. 3.

Most operations of the flash memory system of FIG. 7 are same as those of the conventional flash memory system of FIG. 3, and thus only different operations are described.

The latching and decoding portion 150 receives a sector address, information about the number of sectors, and page address information from the electronic device system and further receives address information of the FRAM cell array 350 as well as address information of the NAND flash memory cell array 35.

The control logic 250 controls the FRAM page buffer portion 450 as well as the NAND flash page buffer portion 45 according to the address ADD and the command COM provided from the latching and decoding portion 150 to read and temporarily store data from the NAND flash memory cell array 35 and the FRAM cell array 350 when the read command is applied.

The FRAM column selecting portion 550 receives a non-volatile memory control signal different from that for the NAND flash column selecting portion 55 from the control logic since the read and write speeds are much faster than those of the NAND flash memory, sequentially the page buffers of the FRAM page buffer portion 450 in a predetermined unit, and then outputs data bits of the selected page buffers.

The buffer portion 650 temporarily stores spare data transferred through the FRAM column selecting portion 550 as well as page data transferred from the NAND flash column selecting portion 55 and outputs data DO stored under control of the control logic 250 when data of one page stored in the FRAM page buffer portion 450 are inputted.

Due to the difference of a data access speed between the NAND flash memory cell array 35 and the FRAM cell array 350, the FRAM cell array 350 serves as the data write and read middle buffer of the NAND flash memory cell array 35 while temporarily storing the booting code information by using the boot loader stored in the spare data cells therein.

The CPU accesses the FRAM cell array 350 which supports a random access and receives the stored booting code to execute the booting program to thereby boot the corresponding operating system of the electronic device system.

At this time, the memory controller 200 controls an overall operation of the flash memory device through the memory bus 60, for example, it provides the address information and the command to the NAND flash memory and the FRAM.

Accordingly, the flash memory device and the flash memory system according to the present invention performs the fast data read operation and writes data without erasing the previous data, having the previous function of the conventional flash memory device “as is”, since the page data are stored in the NAND flash memory cell array 35 and the spare data having the row address as the page data are stored in the FRAM cell array 350.

FIG. 8 illustrates a flash memory device implemented in the form of a multi-chip package according to the exemplary embodiment of the present invention.

As an example of a multi-chip package semiconductor device, a multi-stack semiconductor device 1 in which a plurality of chips (or dies, or wafers) are stacked is shown in FIG. 8. The multi-chip package semiconductor device 1 may include a plurality of chips (or dies, or wafers) CH1 and CH2. And the plurality of chips CH1 and CH2 may have different thicknesses. In FIG. 8, the respective chips CH1 and CH2 may be a flash memory device 100 implemented in one chip and a logic portion 144. For example, the first chip CH1 may be the memory device 100 implemented in one chip, and the second chip CH2 may be the logic portion 144. The logic portion 144 may have the FRAM controller 750 and the FRAM row decoder 850 shown in FIG. 7, and may additionally have a control logic 250. In addition to the logic portion 144, the second chip CH2 may also have a memory controller 200 or a CPU 80. The first chip CH1 includes a plurality of through silicon vias (TSVs) TSV for providing internal connections between the front and rear surfaces of the first chip CH1 itself.

The multi-chip package semiconductor device 1 may include a support substrate SUB for providing power and data connection to the chips of the package. In other words, the first chip CH1 is electrically connected with the support substrate SUB and the second chip CH2 by conductive bumps icon1 and icon2, and may transfer the power and data between the plurality of chips CH1 and CH2 and the support substrate SUB through the TSVs TSV. The support substrate SUB may be a coreless substrate. Although the two chips CH1 and CH2 are stacked on the support substrate SUB in FIG. 8, two or more chips may be stacked. When two or more chips are stacked, two or more chips among the chips may be the same chip. For example, when four chips are stacked, two chips may be the flash memory devices 100 each implemented in one chip, another chip may be the logic portion 144, and the other chip may be the memory controller 200.

FIG. 9 illustrates a TSV of a multi-chip package semiconductor device according to the exemplary embodiment of the present invention. Each of chips 1120 disposed in the middle of a plurality of stacked chips has a conductive bump 1125 and a conductive socket 1115. An upper chip 1130 disposed on the top of the stacked chips may have only the conductive bump 1125 formed on a bond pad 1135, and a lower chip 1110 disposed on the bottom of the stacked chips may have only the conductive socket 1115.

Since FIG. 9 is a cross-sectional view, the shapes and sizes of the conductive bump 1125 and the conductive socket 1115 are not shown. However, the conductive bump 1125 is formed in a cylindrical pillar shape, and the conductive socket 1115 has a recessed shape. Also, the conductive bump 1125 having the cylindrical pillar shape has a size corresponding to the conductive socket 1115. Thus, when the chips 1110 to 1130 are stacked, the conductive bump 1125 is inserted into the conductive socket 1115 and provides a stable conductive connection between the chips 1110 to 1130. The conductive bump 1125 may be formed of copper (Cu) as mentioned above, and the conductive socket 1115 may be formed of an under bump material (UBM) (e.g., nickel/palladium/gold alloy).

FIG. 9 shows a multi-chip package semiconductor device 1100 in which four chips are stacked. However, when two chips are stacked, the upper chip 1130 and the lower chip 1110 may be included.

In the multi-chip semiconductor device 1100 shown in FIG. 9, the two chips 1110 and 1120 of a lower portion may be integrated into one chip as the flash memory device 100, the one chip 1120 may be the logic portion 144, and the upper chip 1130 may be the memory controller 200, as mentioned above. Alternatively, the lower chip 1110 may be the memory controller 200, the two chips 1120 may be integrated into one chip as the flash memory device 100, and the upper chip 1130 may be a CPU. The stacked chips may be diversified.

As shown in FIG. 9, the conductive bump 1125 and the conductive socket 1115 interlock each other, thereby strengthening alignment stability even if stacked chips are moved due to a stack process for the following process (e.g., reflow or underfill). In other words, the conductive bump 1125 and the conductive socket 1115 perform the function of the connectors icon1 and icon2 of FIG. 8. Also, the conductive bump 1125 and the conductive socket 1115 enable a zero bond-line die stack to be formed.

FIG. 10 shows a portion of a chip of FIG. 9, illustrating a conductive pillar including a TSV and a conductive socket in detail.

Each chip includes a substrate 1206 (e.g., a silicon wafer), an annular conductive TSV 1230, and a concave conductive socket 1210. Also, each chip includes a backside passivation layer 1204 and a bond pad 1208. The conductive socket 1210 is formed on the bottom surface of the substrate 1206 and on the internal wall of the annular TSV 1230.

One end of the annular TSV 1230 is formed to be flat. On the flat surface of the TSV 1230, a conductive bump 1310 is formed in the vertical direction. The conductive bump 1310 is arranged to correspond to the conductive socket 1210. Thus, when a plurality of chips are stacked, the conductive bump 1310 is inserted into the conductive socket 1210 so that adjacent chips can be conductively connected.

A passivation layer 1610 may be formed by depositing a passivation material, e.g., aluminum oxide, using, for example, a pulse deposition layer (PDL) process, over the surface of a sidewalls.

In the above description, for easy description, the FRAM has been used as a representative non-volatile memory, but the non-volatile memory is not limited to the FRAM but may comprises PRAM, MRAM, RRAM, and so on.

Also, the exemplary embodiment of the present invention can be applied to a NOR flash memory as well as a NAND flash memory.

As described above, according to the present invention, since the NAND flash memory does not need to have the discrete spare data cell area, a time for mounting the file system of the NAND flash memory on the electronic device system and the booting time are significantly reduced, and since the non-volatile RAM is used as the read and write buffer of the NAND flash memory, an operating performance of the NAND flash memory is improved, and data can be maintained even when powered off.

Accordingly, as described above with respect to FIG. 7, an integrated circuit memory device 100 according to an embodiment of the present invention includes a non-randomly accessible nonvolatile memory 35, which has a first plurality of rows of nonvolatile memory cells therein, and a randomly accessible nonvolatile memory 350, which has a second plurality of rows of nonvolatile memory cells therein. Circuitry is also provided for reading data in parallel from an addressed one of the first plurality of rows and an addressed one of the second plurality of rows, in response to a memory read operation. This circuit, which is electrically coupled to the non-randomly accessible nonvolatile memory 35 and the randomly accessible nonvolatile memory 350, includes a page buffer circuits 45 and 450, column selection circuits 55 and 550 and an output page buffer circuit 650. In this embodiment, the first plurality of rows of nonvolatile memory cells in the non-randomly accessible nonvolatile memory 35 map one-to-one to the second plurality of rows of nonvolatile memory cells the randomly accessible nonvolatile memory 350. The non-randomly accessible nonvolatile memory 35 may be a NAND-type flash memory and the randomly accessible nonvolatile memory 350 may be a memory selected from a group consisting of FRAM, PRAM, MRAM and RRAM.

In the drawings and specification, there have been disclosed typical preferred embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. 

1.-3. (canceled)
 4. A multi-chip package semiconductor device, comprising: a logic chip; and a memory chip comprising a first non-volatile memory having a plurality of memory cells therein configured to store page data, and a second non-volatile memory having a plurality of spare memory cells therein configured to store spare data, wherein the logic chip controls operation of the first non-volatile memory using the second non-volatile memory, wherein the first non-volatile memory and the second non-volatile memory are different types on non-volatile memory.
 5. The multi-chip package semiconductor device of claim 4, wherein the logic chip controls a wear leveling function and a garbage collecting function which are necessary during a write operation of the first non-volatile memory and controls the number of erase times of the first non-volatile memory cell and a block setting of the first non-volatile memory to be deleted.
 6. The multi-chip package semiconductor device of claim 4, wherein the page data are data which have information including the size of data and a file to be written from an external portion and information as to whether data are read or written, and the spare data are data which have information including a boot loader, an error correction code (ECC), information about a bad block, and information about the number of deletion times.
 7. The multi-chip package semiconductor device of claim 4, wherein the first non-volatile memory is a non-randomly accessible non-volatile memory; and wherein the second non-volatile memory is a randomly accessible non-volatile memory.
 8. The multi-chip package semiconductor device of claim 7, wherein the first non-volatile memory is a NAND-type flash memory; and wherein the second non-volatile memory is a memory selected from a group consisting of FRAM, PRAM, MRAM and RRAM.
 9. A semiconductor package comprising: a support substrate to provide power and data connections to a first semiconductor chip; the first semiconductor chip having first circuitry comprising a memory device having a plurality of non-volatile memories of different types from each other, wherein the first semiconductor chip is coupled to the support substrate on a first side of the first semiconductor chip by a first plurality of interconnects, the first semiconductor chip including a first plurality of conductive bumps on a second side thereof; a second semiconductor chip having second circuitry comprising a controller and including a second plurality of conductive bumps, wherein the second semiconductor chip is coupled to the first semiconductor chip by the first and second plurality of conductive bumps.
 10. The semiconductor package of claim 9, wherein the memory device comprise: a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied, wherein the first non-volatile memory and the second non-volatile memory are different types on non-volatile memory.
 11. The semiconductor package of claim 10, wherein the first semiconductor chip includes a plurality of through silicon vias (TSVs) to couple the second semiconductor chip to the support substrate.
 12. The semiconductor package of claim 11, wherein the plurality of TSVs are annular via having recessed portion surrounded by inner walls of the annular via and conductive socket covering the recessed portion.
 13. The semiconductor package of claim 12, wherein the first plurality of conductive bumps and the second plurality of conductive bumps take a form of cylindrical pillar.
 14. The semiconductor package of claim 13, wherein the first plurality of conductive bumps and the second plurality of conductive bumps comprise copper (Cu) bumps.
 15. An apparatus comprising: a first wafer including a first semiconductor chip having first circuitry comprising a memory device having a plurality of non-volatile memories of different types from each other, wherein the first semiconductor chip is to be coupled to a support substrate on a first side of the first semiconductor chip by a first plurality of interconnects, the first semiconductor chip including a first plurality of conductive bumps on a second side thereof and a plurality of through silicon vias (TSVs) to provide interconnections between the first and second sides of the first semiconductor chip; and a second wafer including a second semiconductor chip having second circuitry comprising a processor and including a second plurality of conductive bumps, wherein the second semiconductor chip is coupled to the first semiconductor chip by the first and second plurality of conductive bumps.
 16. The apparatus of claim 15, wherein the memory device comprise: a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied, wherein the first non-volatile memory and the second non-volatile memory are different types on non-volatile memory.
 17. The semiconductor package of claim 16, wherein the first semiconductor chip includes a plurality of through silicon vias (TSVs) to couple the second semiconductor chip to the support substrate.
 18. The semiconductor package of claim 17, wherein the plurality of TSVs are annular via having recessed portion surrounded by inner walls of the annular via and conductive socket covering the recessed portion.
 19. The semiconductor package of claim 18, wherein the first plurality of conductive bumps and the second plurality of conductive bumps take a form of cylindrical pillar.
 20. The semiconductor package of claim 19, wherein the first plurality of conductive bumps and the second plurality of conductive bumps comprise copper (Cu) bumps. 